数字芯片求职

Implemented an RTL-based DVFS controller that dynamically adjusts operating frequency and voltage based on workload

Integrated power gating modules for idle blocks to minimize leakage power

Used clock gating to reduce dynamic power consumption across multiple functional domains

Modeled power-performance trade-offs using Synopsys PrimeTime PX and Design Compiler reports

Built a test environment to emulate real-world scenarios like bursty load, idle periods, and temperature scaling

Analyzed impact of DVFS on memory controller timing and bus synchronization

Deployed RTL design onto a Xilinx Zynq FPGA and conducted real-time power monitoring using onboard ADC

Created detailed technical documentation outlining DVFS states, transitions, and control policies

Worked with physical design team to propagate power intent using UPF constraints

Supported validation engineers during regression testing and silicon bring-up simulation

Developed a reusable UVM testbench environment for verifying RISC-V SoC functional correctness

Implemented constrained-random and directed test sequences for core modules including ALU, load/store unit, and interrupt controller

Created coverage models (functional and code) to measure test effectiveness and identify corner cases

Used SystemVerilog assertions (SVA) to detect protocol violations and unexpected behaviors

Integrated the testbench with a SystemVerilog DPI-C interface to run compliance tests from the Spike RISC-V simulator

Debugged failing tests using waveform analysis in QuestaSim and resolved issues through detailed waveform tracing

Coordinated with RTL designers to triage functional mismatches and propose fixes

Executed regression testing across multiple clock configurations and reset conditions

Automated test runs and coverage reports using scripts in Python and Make

Participated in weekly sync-ups with design and verification teams to report status and align verification plans

Led RTL implementation of a 7-stage pipelined RISC-V CPU core using SystemVerilog, achieving precise exception handling through hazard detection optimization and modular CSR register design supporting RV32IM extensions.

Developed UVM verification environment with virtual sequence-based test scenarios, creating directed test suites for multi-core cache coherence (MESI) protocols and cross-clock domain signal integrity validation.

Integrated JasperGold formal verification to prove instruction prefetch module properties, resolving control flow conflicts through SVA assertion libraries covering pipeline hazard scenarios.

Built Python-driven regression framework with Synopsys VCS optimizations, enabling distributed test scheduling on AWS Batch for parallel RTL version validation.

Implemented UPF 3.0 multi-voltage domain design with hybrid clock gating/power gating strategies through power state machine modeling.

Deployed GitLab CI/CD pipeline integrating SpyGlass CDC/RDC checks and Design Compiler topological analysis, generating interactive timing constraint reports for architectural optimization.

Developed configurable TPU subsystem using Chisel HDL, supporting dynamic precision switching (INT4/INT8/FP16) through parameterized systolic array generation engine.

Designed AXI4-Stream multi-stage DMA controller with SystemC TLM 2.0 bandwidth simulation, optimizing data path priority arbitration algorithms.

Created UVM verification platform with Python-based AI workload generator, implementing end-to- end result validation between PyTorch models and RTL via DPI-C interfaces.

Conducted low-power verification using Synopsys VC LP, establishing power state coverage groups for IP wakeup/sleep protocol compliance.

Implemented Clang-based RTL documentation system with custom annotations, generating interactive waveform diagrams and IP integration manuals in multi-format outputs.

Built Xilinx Vitis emulation environment integrated with Synopsys Verdi protocol analyzer, enabling real-time performance heatmap visualization for AI inference tasks.